1. Field of the Invention
The present invention relates to sequential state machines and particularly to the methods and apparatus for providing a programmable interface to these machines.
2. Description of Background Art
Existing techniques used in designing finite state machines require that the nature and all possible variations of the state machine interface be known in advance. What is needed is a method and apparatus that can be used to build interfaces between components whose interface waveform characteristics are not known in advance; i.e., the state machine is required to interface with different kinds of devices whose interface waveforms are not identical. Often times, even different manufacture's versions of the same kind of devices are not identical. This requires that register transfer level (RTL) logic be coded into the state machine to handle the appropriate interface. As a result, there is limited programmability for modifying the state machine behavior.
FIG. 1 shows the bit assignment of a control register 10 and its clock waveform 11 for a typical state machine interface (SMI). As illustrated, the design of a state machine interface is usually based around access cycles, which is defined as the period of time during which the pins on the interface repeat a sequence of events. This sequence may be anything the designer chooses and as mentioned earlier, is often established using RTL coded circuitry. The control register 10 shown has 32-bits and counts DOWN from B31 to B0, although this register could have any number of bits and could also just as well count UP.
Each input and output of the interface is controlled by one or more of these control registers 10 on a cycle-by-cycle basis. Each bit in the register corresponds to one clock 11 cycle. The state, using the registers 10, can be changed on either the leading (positive) edge (as shown) or the trailing (negative) edge of the clock 11. For example, in the case of the output control register 10, a binary 1 in location B31 will cause the state machine output pin to go HIGH on the positive edge of the first clock cycle in the access cycle, and a binary 0 in location B30 will cause the output to go LOW during the second clock cycle in the access cycle, and so forth. Although the largest access cycle supported in this example is 32 clock cycles, this can be any size.
State machines are required to start each cycle at a predictable point in time, shown as the ‘begin new access cycle’ in FIG. 1, in order to properly synchronize the state machine with the interface it is “talking” to. This synchronization can be such that the state machine is configured as a slave or as the master.
When the state machine is configured as a slave, it uses an external input strobe from the application device to determine the clock cycle at which a new access cycle should begin. The synchronization can occur on either the positive or negative edge of the strobe pulse signal. Alternatively, synchronization can be chosen to occur when the strobe is HIGH or LOW for applications such as FIFO interfaces, where any state machine accessing the FIFO may have to start or stop depending on the state of an “empty” or “full” signal.
On the other hand, in the case where the state machine is the master, placing the burden of synchronization on the application device, the strobe input pin can be inhibited by connecting it to a suitable voltage level.
What is needed is a state machine interface that is completely programmable for use with any device without apriori knowledge of the detailed specifics of the device. The state machine interface disclosed herein addresses this need by providing an interface that can be programmed for use with multiple non-compatible devices.